Recently, a great deal of research and development (R&D) efforts are made on the semiconductor package. The conventional 2D (two-dimensional) package technology is now stepping forward to 2.5-D (two and a half-dimensional) or 3-D (three-dimensional) package technology. The R&D trend moves to the direction of utilizing both the inside of the substrate and the 3-D space above the substrate from the conventional technology of embedding the chip only on the board.
The embedding technology attracts a great deal of attention in the leading-edge PCB industry because it reduces the packaging space and efficiently integrates the die stack.
FIGS. 1a, 1b, and 1c are diagrams illustrating the cavity wherein the semiconductor chip is embedded according to the prior art.
Referring to FIGS. 1a and 1b, we need to perform a laser drill on the PREPREG 5 in order to fabricate a cavity 10 in accordance with the prior art. Since the bottom surface of the cavity tends to be inevitably non-flat when the laser drill is applied, it is not easy to directly mount the semiconductor chip 30 on the bottom surface of the cavity. In order to resolve this problem, a copper layer 20 is prepared on the PREPREG in order to avoid damage on the surface of the PREPREG during the laser drill.
In other words, it is difficult to mount the semiconductor chip on the surface of the cavity due to the failure of surface flatness if the bottom surface of the cavity is severely damaged during the laser drill.
However, if you mount the semiconductor chip 30 on the copper barrier according to the prior art, you may succeed to embed the chip 30 just inside the cavity, but failed to make direct electrical contacts such as flip-chip bonding between the chip electrodes and the pads on the package substrate. Therefore, the prior art relies on the wire bonding technology between the pad of the upper surface of the chip and the pads on the package substrate.
Recently, the number of I/O terminals has so tremendously increased that we will need a huge number, therefore a huge area for bonding pads if we adopt only the wire bonding technology, which will consequently increase the package size as well as the packaging cost. Furthermore, as shown in FIG. 1c, if you want to realize a die stack, it is more difficult to make electrical contacts.
Therefore, it is urgently needed to make flip-chip bonding possible by preparing the bump pads on the bottom surface of the cavity. We can think about a method of coating the etch mask on the copper barrier 20 and making bump pads by the selective etch. However, this method is not recommended because the bump pads are easily peeled off due to the non-uniformity of resin etching between the pads as well as non-uniformity in the resin depth of the bump.